Chip dicing & packaging

Nano to Micro/Macro (Micro-fabrication)

Chip packaging is the last process in the fabrication flow of an micro-nanodevice. It consists in the chip insertion in a substrate aimed to:

a)      Make the chip functions easily accessible (electrical connection with the real world),

b)      facilitate its handling for its assembly onto an electronic system

c)       preserve the chip from external agents and increase its durability.

Hence the importance of the packaging in the final behavior of a device or circuit is very high, since the packaging can heavily affect the yield and performance of the device in several aspects as its thermal dissipation capability, its electrostatic discharge resistance or its number of outside connections.

Several important steps of the packaging process can be distinguished: the substrate (silicon or others) dicing with manual or automatic saws, the die attach by manual or automatic pick and place or flip-chip techniques, the electrical connection (wedge, ball and ribbon bonding with different wire materials and diameters) and the final encapsulation and package quality test (die shear and pull test).

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          provided at NFFA-Europe laboratories by:
CSIC-CNM
Spain
INESC-MN
Portugal
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          provided by:
EURONANOLAB
France
CSIC-CNM
Spain
K&S 4xxx Series
Ultrasonic wire bonding (wedge)
Al and Au wires
Al wires diameter: 0.7mills – 15mills Au wires diam.: 1mill - 2mills
Square contacting pads sized 4 times the wire diameter
Positioning fully manual
Max size of the dice: 10cm x 10cm Contacting pads of Al or Au
Clean room environment
Optical microscopes and ball bonding option capability
CSIC-CNM
Spain
LoadPoint 3AV14 / K&S 980-10
Solid substrates sawing Wafer dicing
Resin bonded diamond blade / Ni-diamond blade
Speed rotation up to 40000 rpm
y-axis: 2 microns (mm) J-axis: 1º Minimum Kerf down to 35 microns
Semi-automatic wafer positioning
Wafers up to 8” diameter and 2,5mm thickness Materials: Si, borosilicates, ceramics, SiC and Safire